The present invention relates to electronics circuits, and more particularly to an interface circuit that provides an analog signal having an adjustable time response.
A digital-to-analog interface circuit is commonly used in many electronics circuits to provide an analog signal that drives an analog circuit element. The interface circuit typically employs a pulse width modulator (PWM) or a pulse density modulator (PDM) that receives a digital signal from a digital circuit and generates a corresponding intermediate signal that is filtered to provide the analog signal. The PWM or PDM act as an interface between the digital and analog circuits.
A conventional PWM or PDM receives a digital signal comprising a sequence of N-bit digital values and for each value generates a corresponding waveform. Each waveform has a predetermined period and includes a number of high ("1") and low ("0") values, as determined by the input digital value. For example, for a 9-bit PWM or PDM, the input digital value can range from 0 through 511 and each waveform has a period of 512 clock cycles and includes 0 to 511 high values. An input digital value of 128, for example, corresponds to a waveform having 128 high values and 384 low values. For a PWM, the high values are grouped together at the start of each waveform and for a PDM the high values are somewhat randomly spread across the waveform. For ease of implementation, some PDMs spread the high values in a pseudo-random manner, and not uniformly. The waveforms are digital in nature and are filtered to generate the analog signal.
One common application for the interface circuit is in control loops. For example, for a receiver or a transmitter in a communications system, the interface circuit can be used for a carrier tracking loop, a bit timing loop, an automatic gain control (AGC) loop, a bias control loop, a power control loop, a DC offset adjustment loop, and others. For each of these loops, a loop control circuit generates a digital control signal that is provided to a PWM or PDM within the interface circuit associated with that loop. The PWM or PDM generates a sequence of waveforms based on the values in the digital control signal. The waveforms are filtered to generate the analog control signal that is used to drive the controlled element (e.g., a voltage-controlled oscillator, a variable gain amplifier, a summing element, and so on).
The analog control signals generated in conjunction with the PWMs or PDMs are typically required to meet various specifications. Typical specifications include a response time (i.e., the settling time) for a step input and ripple amplitude on the control signal. Fast response time and small amounts of ripple are desirable (or required) for many applications. The fast response time allows for a wide bandwidth control loop and a quick response to rapid changes in the input condition. The ripples on the control signal correspond to noise, and small amounts of ripple are generally required for better performance. However, fast response time and small amounts of ripple are conflicting design considerations. Optimizing for fast response time often results in larger ripple amplitude on the control signal.
As can be seen, an interface circuit having adjustable time response (i.e., to provide a faster response time) while maintaining small ripple amplitude is highly desirable.